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Revisiting ILP Designs for Throughput-Oriented GPGPU Architecture.

, , , , and . CCGRID, page 121-130. IEEE Computer Society, (2015)

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Generating GPU Compiler Heuristics using Reinforcement Learning., , and . CoRR, (2021)AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators., , , , , , , , and . CGO, page 143-157. IEEE, (2024)Airavat: Improving energy efficiency of heterogeneous applications., , , , and . DATE, page 731-736. IEEE, (2018)Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement., , , , , and . ICS, page 433-442. ACM, (2013)ArmorAll: Compiler-based Resilience Targeting GPU Applications., , , and . ACM Trans. Archit. Code Optim., 17 (2): 9:1-9:24 (2020)Many-thread aware instruction-level parallelism: architecting shader cores for GPU computing., , , , and . PACT, page 449-450. ACM, (2012)Moka: Model-based concurrent kernel analysis., , , , , and . IISWC, page 197-206. IEEE Computer Society, (2017)AXI4MLIR: User-Driven Automatic Host Code Generation for Custom AXI-Based Accelerators., , , , , , , , and . CoRR, (2023)Shared memory multiplexing: a novel way to improve GPGPU throughput., , , , and . PACT, page 283-292. ACM, (2012)Revisiting ILP Designs for Throughput-Oriented GPGPU Architecture., , , , and . CCGRID, page 121-130. IEEE Computer Society, (2015)