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Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices.

S. Lim, J. Bae, J. Eum, S. Lee, C. Kim, B. Park, and J. Lee. CoRR, (2017)

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Jong-Dae Bae

Jeong-Ho Bae

Jong Ho Pee

Jong Ho Lim

Ho Jong Lee

Other publications of authors with the same name

Short- and Long-Term Memory Based on a Floating-Gate IGZO Synaptic Transistor.D. Kang, W. Kim, J. Jang, C. Kim, J. Kim, S. Choi, J. Bae, D. Kim, Y. Kim, and D. Kim. IEEE Access, (2023)Improvement of the Symmetry and Linearity of Synaptic Weight Update by Combining the InGaZnO Synaptic Transistor and Memristor.T. Yang, J. Cho, H. Lee, H. Lee, S. Myoung, D. Lee, S. Choi, J. Bae, D. Kim, C. Kim and 2 other author(s). IEEE Access, (2024)Pulse-Width Modulation Neuron Implemented by Single Positive-Feedback Device.S. Woo, D. Kwon, B. Park, J. Lee, and J. Bae. CoRR, (2021)Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices.S. Lim, J. Bae, J. Eum, S. Lee, C. Kim, B. Park, and J. Lee. CoRR, (2017)A Spiking Neural Network with a Global Self-Controller for Unsupervised Learning Based on Spike-Timing-Dependent Plasticity Using Flash Memory Synaptic Devices.W. Kang, C. Kim, S. Lee, S. Woo, J. Bae, B. Park, and J. Lee. IJCNN, page 1-7. IEEE, (2019)Review of candidate devices for neuromorphic applications.J. Lee, Y. Noh, H. Kim, J. Kim, J. Bae, S. Woo, S. Lee, S. Lim, W. Kang, Y. Seo and 3 other author(s). ESSDERC, page 22-27. IEEE, (2019)Si-Based Dual-Gate Field-Effect Transistor Array for Low-Power On-Chip Trainable Hardware Neural Networks.K. Lee, D. Kwon, I. Lee, J. Hwang, J. Im, J. Bae, W. Choi, S. Woo, and J. Lee. Adv. Intell. Syst., (January 2024)On-chip trainable hardware-based deep Q-networks approximating a backpropagation algorithm.J. Kim, D. Kwon, S. Woo, W. Kang, S. Lee, S. Oh, C. Kim, J. Bae, B. Park, and J. Lee. Neural Comput. Appl., 33 (15): 9391-9402 (2021)Investigation of Neural Networks Using Synapse Arrays Based on Gated Schottky Diodes.S. Lim, D. Kwon, S. Lee, H. Kim, J. Bae, and J. Lee. IJCNN, page 1-8. IEEE, (2019)Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems.S. Woo, D. Kwon, N. Choi, W. Kang, Y. Seo, M. Park, J. Bae, B. Park, and J. Lee. IEEE Access, (2020)

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Disambiguation of "Bae, Jong-Ho"

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Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices.

Please choose a person to relate this publication to

Jong-Dae Bae

Jeong-Ho Bae

Jong Ho Pee

Jong Ho Lim

Ho Jong Lee

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bae, Jong-Ho"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices.

Please choose a person to relate this publication to

Jong-Dae Bae

Jeong-Ho Bae

Jong Ho Pee

Jong Ho Lim

Ho Jong Lee

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices.