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Network Insensitivity to Parameter Noise via Parameter Attack During Training.

, , and . ICLR, OpenReview.net, (2022)

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Programming Weights to Analog In-Memory Computing Cores by Direct Minimization of the Matrix-Vector Multiplication Error., , , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 13 (4): 1052-1061 (December 2023)Network Insensitivity to Parameter Noise via Parameter Attack During Training., , and . ICLR, OpenReview.net, (2022)Ladder Networks for Semi-Supervised Hyperspectral Image Classification., and . CoRR, (2018)A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference., , , , , , , , , and 19 other author(s). CoRR, (2022)AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator., , , , , , , , , and . CoRR, (2021)Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inference., , , , , , , , , and 1 other author(s). CoRR, (2023)Improving the Accuracy of Analog-Based In-Memory Computing Accelerators Post-Training., , , , , , and . CoRR, (2024)Network insensitivity to parameter noise via adversarial regularization., , and . CoRR, (2021)ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator., , , , , , , , , and . IEEE Micro, 42 (6): 76-87 (2022)Gradient descent-based programming of analog in-memory computing cores., , , , , , , , , and 4 other author(s). CoRR, (2023)