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Novel Built-In Current-Sensor-Based IDDQ Testing Scheme for CMOS Integrated Circuits.

, , and . IEEE Trans. Instrumentation and Measurement, 58 (7): 2196-2208 (2009)

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Novel Built-In Current-Sensor-Based IDDQ Testing Scheme for CMOS Integrated Circuits., , and . IEEE Trans. Instrumentation and Measurement, 58 (7): 2196-2208 (2009)New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (2): 377-384 (2006)A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications., and . J. Signal Process. Syst., 52 (3): 211-229 (2008)ECC Caching Techniques for Protecting NAND Flash Memories., , , and . ITC-Asia, page 47-52. IEEE, (2020)Back-End-of-Line Defect Analysis for Rnv8T Nonvolatile SRAM., , , , , , , and . Asian Test Symposium, page 123-127. IEEE Computer Society, (2013)Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications., , , and . DFT, page 136-143. IEEE Computer Society, (2010)A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip., and . DFT, page 122-128. IEEE Computer Society, (2010)Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder., , , and . IEEE Trans. Computers, 60 (5): 628-638 (2011)High-performance 3D-SRAM architecture design., and . APCCAS, page 907-910. IEEE, (2010)Design of Low-Frequency Low-Pass Filters for Biomedical Applications., , , and . APCCAS, page 690-695. IEEE, (2006)