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Power-Aware High-Level Synthesis With Clock Skew Management., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 167-171 (2012)High-level test synthesis for delay fault testability., and . DATE, page 45-50. EDA Consortium, San Jose, CA, USA, (2007)Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications., , , , , , and . SoCC, page 286-291. IEEE, (2014)Thermal Safe High Level Test Synthesis for Hierarchical Testability., and . Asian Test Symposium, page 337-342. IEEE Computer Society, (2010)High-level low-power system design optimization., and . VLSI-DAT, page 1-4. IEEE, (2017)