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Disambiguation of "Koide, Tetsushi"

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Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search.

, , , , and . APCCAS, page 1309-1312. IEEE, (2006)

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Tetsushi Hirano

Tetsushi Harada

 

Other publications of authors with the same name

FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification., , , , , , , , , and 3 other author(s). APCCAS, page 651-654. IEEE, (2014)Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline., , , , , and . APCCAS, page 1297-1300. IEEE, (2006)An MCM Routing Algorithm Considering Crosstalk., , , and . ISCAS, page 211-214. IEEE, (1995)Genetic algorithm accelerator GAA-II., , , , and . ASP-DAC, page 9-10. ACM, (2000)Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding., , and . ICNC, page 15-19. IEEE Computer Society, (2010)Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size., , , , and . ICNC, page 128-132. IEEE Computer Society, (2010)Sweat Droplets Detection Using Image Segmentation on Skin Surface for Evaluation of Sweating Responses to Thermal Stimulus in Atopic Dermatitis., , , , and . MWSCAS, page 559-562. IEEE, (2021)Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping., , , , and . ESSCIRC, page 538-541. IEEE, (2010)A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme., , , , and . ESSCIRC, page 320-323. IEEE, (2007)A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout., and . ASP-DAC, page 577-583. IEEE, (1998)