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Disambiguation of "Lim, Sung Kyu"

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How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions.

, , , , and . ISLPED, page 320-325. ACM, (2016)

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Sung-Ki Lim

Yong-Sung Lim

Han-Sung Lim

Sung-Kyu Hong

Sung-Yeun Lim

 

Other publications of authors with the same name

Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs., , , , , and . DATE, page 37-42. IEEE, (2020)Partitioning and placement for buildable QCA circuits., , and . ACM J. Emerg. Technol. Comput. Syst., 1 (1): 50-72 (2005)Distributed TSV Topology for 3-D Power-Supply Networks., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (11): 2066-2079 (2012)Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (4): 605-616 (2021)Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches., , , and . Microprocess. Microsystems, (2016)Edge separability-based circuit clustering with application to multilevel circuit partitioning., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (3): 346-357 (2004)Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (11): 1694-1707 (2013)Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (12): 1964-1976 (2015)TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (8): 1194-1207 (2012)Retiming-based timing analysis with an application to mincut-based global placement., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (12): 1684-1692 (2004)