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Disambiguation of "Huang, Shi-Yu"

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Graph Neural Networks for Charged Particle Tracking on FPGAs.

, , , , , , , , , , , , , , and . Frontiers Big Data, (2022)

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Yu Shi

Shi-Ming Huang

Yu-E Shi

Yu-Hwa Huang

Yu-Han Huang

 

Other publications of authors with the same name

At-speed BIST for interposer wires supporting on-the-spot diagnosis., , , and . IOLTS, page 67-72. IEEE, (2013)Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (4): 908-917 (2013)High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction., , , and . IEEE Trans. Circuits Syst. Video Techn., 22 (3): 340-351 (2012)A Light-and-Fast SLAM Algorithm for Robots in Indoor Environments Using Line Segment Map., , , and . J. Robotics, (2011)General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (11): 1836-1846 (2015)Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (12): 2039-2048 (2015)Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 3044-3055 (2020)Cloud-Based Online Ageing Monitoring for IoT Devices., , and . IEEE Access, (2019)Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (8): 2761-2765 (2023)AutoFix: a hybrid tool for automatic logic rectification., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (9): 1376-1384 (1999)