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Generating Efficient FPGA-based CNN Accelerators from High-Level Descriptions., , , and . J. Signal Process. Syst., 94 (10): 945-960 (2022)A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC., , , , , , , , , and 3 other author(s). ESSCIRC, page 57-60. IEEE, (2013)SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency., , , , , , , , , and 11 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 49 (7): 1475-1486 (2014)Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators., , , and . SiPS, page 123-128. IEEE, (2021)SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration., , , , , , , , , and 10 other author(s). CoRR, (2023)PNeuro: A scalable energy-efficient programmable hardware accelerator for neural networks., , , , , , , , and . DATE, page 1039-1044. IEEE, (2018)Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems., , , , and . SiPS, page 1-6. IEEE, (2020)A Self-reconfigurable FPGA-Based Platform for Prototyping Future Pervasive Systems., , and . ICES, volume 6274 of Lecture Notes in Computer Science, page 262-273. Springer, (2010)