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Extern Objects in P4: an ROHC Header Compression Scheme Case Study., , , и . NetSoft, стр. 517-522. IEEE, (2018)A high-speed traffic manager architecture for flow-based networking., , и . NEWCAS, стр. 161-164. IEEE, (2017)Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis., , и . ISCAS, стр. 1-5. IEEE, (2018)An efficient verification method for a class of multi-phase sequential circuits., , и . ICECS, стр. 510-515. IEEE, (2000)HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches., , и . NEWCAS, стр. 229-233. IEEE, (2018)A fast systolic priority queue architecture for a flow-based Traffic Manager., , , и . NEWCAS, стр. 1-4. IEEE, (2016)A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue., , и . IEEE Trans. Very Large Scale Integr. Syst., 26 (10): 1939-1952 (2018)P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs., , и . FPGA, стр. 147-152. ACM, (2018)Design of low power 4-bit flash ADC based on standard cells., , и . NEWCAS, стр. 1-4. IEEE, (2013)Extern Objects in P4: an ROHC Compression Case Study., , , и . CoRR, (2016)