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A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 46 (1): 107-118 (2011)A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction., , , , , , , , , and 20 other author(s). ISSCC, page 434-435. IEEE, (2010)QE BERT: Bilingual BERT Using Multi-task Learning for Neural Quality Estimation., , , and . WMT (3), page 85-89. Association for Computational Linguistics, (2019)Video Indexing and Retrieval using the Cauchy Function and the Modified Hausdorff Distance., , and . SIP, page 309-314. IASTED/ACTA Press, (2003)Genome sequence of the hot pepper provides insights into the evolution of pungency in Capsicum species, , , , , , , , , and 61 other author(s). Nat. Genet., (2014)A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 53 (1): 124-133 (2018)The Effect of Presentation on Visual Working Memory., , and . HCI (26), volume 434 of Communications in Computer and Information Science, page 346-350. Springer, (2014)An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion., , , , , , , , , and 19 other author(s). ISSCC, page 492-617. IEEE, (2007)Optimal determination of force field parameters for reduced molecular dynamics model., , , and . Comput. Phys. Commun., (2019)An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 43 (1): 121-131 (2008)