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Disambiguation of "Chang, Tsung-Yung Jonathan"

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RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator.

, , , , , , , , , , , , and . IEEE J. Solid State Circuits, 56 (4): 1105-1115 (2021)

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Tsung-ming Chang

Tsung-Tung Chang

Tsung-Tung Chang

Tsung-Tung Chang

Tsung-Tung Chang

 

Other publications of authors with the same name

A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application., , , , and . A-SSCC, page 9-12. IEEE, (2017)11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme., , , , and . ISSCC, page 200-201. IEEE, (2017)A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications., , , , , , , , and . VLSI Technology and Circuits, page 24-25. IEEE, (2022)An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices., , , , , , , , , and 4 other author(s). ISSCC, page 1-3. IEEE, (2022)Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs., , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity., , , , , , , , , and 8 other author(s). ISSCC, page 494-495. IEEE, (2023)34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell., , , , , , , , , and 13 other author(s). ISSCC, page 572-574. IEEE, (2024)