Author of the publication

Design of Clock Distribution Networks in Presence of Process Variations.

, , and . Great Lakes Symposium on VLSI, page 95-102. IEEE Computer Society, (1998)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications., and . ISCAS (5), page 101-104. IEEE, (2002)On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (1): 322-335 (2008)Optimal partitioning of globally asychronous locally synchronous processor arrays., , and . ACM Great Lakes Symposium on VLSI, page 7-12. ACM, (2004)Design of Clock Distribution Networks in Presence of Process Variations., , and . Great Lakes Symposium on VLSI, page 95-102. IEEE Computer Society, (1998)A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms., , and . ISCAS (4), page 3343-3346. IEEE, (2005)Parallel Regeneration of Interconnections in VLSI & ULSI Circuits., and . ISCAS, page 2023-2026. IEEE, (1993)A Fast Low-Power Driver for Long Interconnections in VLSI Systems., , and . ISCAS, page 343-346. IEEE, (1994)Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (10): 1637-1643 (2005)Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations., , and . IEEE Trans. Very Large Scale Integr. Syst., 5 (2): 161-174 (1997)A novel theory on parallel repeater-insertion methodologies for long on-chip interconnects., , and . I. J. Circuit Theory and Applications, 40 (7): 693-708 (2012)