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Enabling Cache Coherency for N-Way SMP Systems on Programmable Chips.

, , and . ERSA, page 312. CSREA Press, (2004)

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FPGA technology mapping with encoded libraries andstaged priority cuts., , , , and . FPGA, page 143-150. ACM, (2009)Power minimisation during field programmable gate array placement., , , , , , and . IET Comput. Digit. Tech., 4 (3): 170-183 (2010)FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (9): 1305-1318 (2012)Improving Timing-Driven FPGA Packing With Physical Information., , and . FPL, page 117-123. IEEE, (2007)ICCAD-2017 CAD contest in multi-deck standard cell legalization and benchmarks., , , and . ICCAD, page 867-871. IEEE, (2017)An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only)., , , and . FPGA, page 266. ACM, (2015)Eh?Placer: A High-Performance Modern Technology-Driven Placer., , , , and . ACM Trans. Design Autom. Electr. Syst., 21 (3): 37:1-37:27 (2016)A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement., , , and . ISPD, page 141-148. ACM, (2017)Mixed-size placement via line search., and . ICCAD, page 899-904. IEEE Computer Society, (2005)Engineering details of a stable force-directed placer., , and . ICCAD, page 573-580. IEEE Computer Society / ACM, (2004)