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Disambiguation of "Wu, An-Yeu"

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Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems.

, , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (11): 1245-1249 (2006)

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Changseon Yeum

Danny Yeung

Thomas Yeung

Kam Yeung

Maureen W Yeung

 

Other publications of authors with the same name

Entropy-Assisted Multi-Modal Emotion Recognition Framework Based on Physiological Signals., , , , and . CoRR, (2018)A memory-reduced log-MAP kernel for turbo decoder., , and . ISCAS (2), page 1032-1035. IEEE, (2005)On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems., , , and . SiPS, page 422-427. IEEE, (2006)Low-complexity Recurrent Neural Network-based Polar Decoder with Weight Quantization Mechanism., , , and . CoRR, (2018)Unsupervised Learning for Neural Network-based Polar Decoder via Syndrome Loss., and . CoRR, (2019)A Reduced-Complexity Fast Algorithm for Software Implementation of the IFFT/FFT in DMT Systems., , and . EURASIP J. Adv. Signal Process., 2002 (9): 961-974 (2002)An 8.29 mm2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process., , , and . IEEE J. Solid State Circuits, 43 (3): 672-683 (2008)Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules., , , and . ISCAS, page 869-872. IEEE, (2007)VLSI design of dual-mode Viterbi/turbo decoder for 3GPP., , , and . ISCAS (2), page 773-776. IEEE, (2004)New Ping-Pong Scheduling for Low-Latency EMD Engine Design in Hilbert-Huang Transform., , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (8): 532-536 (2013)