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Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster.

P. Paolucci, R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, E. Pastorelli, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)

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Piero Kirchner

Multiplex-System für digitale Datenströme in multimedialen AnwendungenP. Kirchner. TU Ilmenau, (2009)

Piero Zappi

Piero Domizi

Piero Giansanti

Johannes Pieroth

Other publications of authors with the same name

The APE-100 Computer: (I) the Architecture.C. Battista, S. Cabasino, F. Marzano, P. Paolucci, J. Pech, F. Rapuano, R. Sarno, G. Todesco, M. Torelli, W. Tross and 10 other author(s). Int. J. High Speed Comput., 5 (4): 637-656 (1993)Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster.P. Paolucci, R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, E. Pastorelli, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. ReConFig, page 1-6. IEEE, (2013)ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.R. Ammendola, A. Biagioni, O. Frezza, W. Geurts, G. Goossens, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula and 2 other author(s). Future Gener. Comput. Syst., (2015)APENet: a high speed, low latency 3D interconnect network.R. Ammendola, M. Guagnelli, G. Mazza, F. Palombi, R. Petronzio, D. Rossetti, A. Salamon, and P. Vicini. CLUSTER, page 481. IEEE Computer Society, (2004)Real-Time Cortical Simulations: Energy and Interconnect Scaling on Distributed Systems.F. Simula, E. Pastorelli, P. Paolucci, M. Martinelli, A. Lonardo, A. Biagioni, C. Capone, F. Capuani, P. Cretaro, G. Bonis and 4 other author(s). PDP, page 283-290. IEEE, (2019)Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. FPT, page 58-65. IEEE, (2013)apeNEXT: a Multi-TFlops Computer for Elementary Particle Physics.F. Bodin, P. Boucaud, N. Cabibbo, F. Carlo, R. Pietri, F. Renzo, H. Kaldass, A. Lonardo, M. Lukyanov, S. de Luca and 11 other author(s). PARCO, volume 13 of Advances in Parallel Computing, page 355-362. Elsevier, (2003)NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs.R. Ammendola, A. Biagioni, O. Frezza, G. Lamanna, A. Lonardo, F. Cicero, P. Paolucci, F. Pantaleo, D. Rossetti, F. Simula and 3 other author(s). CoRR, (2013)Impact of exponential long range and Gaussian short range lateral connectivity on the distributed simulation of neural networks including up to 30 billion synapses.E. Pastorelli, P. Paolucci, R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, M. Martinelli, F. Simula, and P. Vicini. CoRR, (2015)

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Disambiguation of "Vicini, Piero"