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Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs.

C. Lung, Y. Su, H. Huang, Y. Shi, and S. Chang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (7): 1100-1109 (2013)

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Yiyu Chen

Huili Shi

Lei Shi

Zhanjun Shi

Jian Shi

Other publications of authors with the same name

Partial Unbalanced Feature Transport for Cross-Modality Cardiac Image Segmentation.S. Dong, Z. Pan, Y. Fu, D. Xu, K. Shi, Q. Yang, Y. Shi, and C. Zhuo. IEEE Trans. Medical Imaging, 42 (6): 1758-1773 (June 2023)Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling.H. Yu, C. Chu, Y. Shi, D. Smart, L. He, and S. Tan. IEEE Trans. Very Large Scale Integr. Syst., 18 (10): 1399-1411 (2010)The importance of resource awareness in artificial intelligence for healthcare.Z. Jia, J. Chen, X. Xu, J. Kheir, J. Hu, H. Xiao, S. Peng, X. Hu, D. Chen, and Y. Shi. Nat. Mac. Intell., 5 (7): 687-698 (July 2023)Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs.C. Lung, Y. Su, H. Huang, Y. Shi, and S. Chang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (7): 1100-1109 (2013)Accelerating Dynamic Time Warping With Memristor-Based Customized Fabrics.X. Xu, F. Lin, A. Wang, X. Yao, Q. Lu, W. Xu, Y. Shi, and Y. Hu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (4): 729-741 (2018)Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations.Y. Shi, J. Xiong, C. Liu, and L. He. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (7): 1253-1263 (2008)Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking.U. Tida, C. Zhuo, L. Liu, and Y. Shi. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (2): 281-293 (2020)On Random Dynamic Voltage Scaling for Internet-of-Things: A Game-Theoretic Approach.H. Geng, K. Kwiat, C. Kamhoua, and Y. Shi. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (1): 123-132 (2018)Fast Random Walk Based Capacitance Extraction for the 3-D IC Structures With Cylindrical Inter-Tier-Vias.C. Zhang, W. Yu, Q. Wang, and Y. Shi. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (12): 1977-1990 (2015)Hardware/Software Co-Exploration of Neural Architectures.W. Jiang, L. Yang, E. Sha, Q. Zhuge, S. Gu, S. Dasgupta, Y. Shi, and J. Hu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 4805-4815 (2020)

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Disambiguation of "Shi, Yiyu"

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Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs.

Please choose a person to relate this publication to

Yiyu Chen

Huili Shi

Lei Shi

Zhanjun Shi

Jian Shi

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Shi, Yiyu"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs.

Please choose a person to relate this publication to

Yiyu Chen

Huili Shi

Lei Shi

Zhanjun Shi

Jian Shi

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs.