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A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment.

, , , , and . FCCM, page 184-191. IEEE Computer Society, (2016)

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Track finding mezzanine for Level-1 triggering in HL-LHC experiments., , , , , , , , , and 10 other author(s). MOCAST, page 1-4. IEEE, (2017)A novel FPGA-based track reconstruction approach for the level-1 trigger of the CMS experiment at CERN., , , , , , , , , and 22 other author(s). FPL, page 1-4. IEEE, (2017)First Evaluation of FPGA Reconfiguration for 3D Ultrasound Computer Tomography., , , , , and . ReCoSoC, volume 7551 of KIT Scientific Reports, page 109-114. KIT Scientific Publishing, (2010)Evaluation of performance and architectural efficiency of FPGAs and GPUs in the 40 and 28 nm generations for algorithms in 3D ultrasound computer tomography., , , and . Comput. Electr. Eng., 40 (4): 1171-1185 (2014)Online data reduction with a DSP-FPGA multiprocessor system., and . DSP, page 819-822. IEEE, (2002)A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique., , , and . SoCC, page 206-212. IEEE, (2018)Online data reduction with a DSP-FPGA multiprocessor system., and . ISSPA, page 619-622. IEEE, (2001)DSP-FPGA multiprocessor system with CAN, PPI, and ethernet interfaces., and . Circuits, Signals, and Systems, page 264-269. IASTED/ACTA Press, (2005)