Author of the publication

Graphics processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithm.

, , and . ISCAS (5), page 265-268. IEEE, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A bit serial LDI recursive digital filter., , and . ICASSP, page 238-241. IEEE, (1984)An FPGA implementation of a matched filter detector for spread spectrum communications systems., , , , and . FPL, volume 1304 of Lecture Notes in Computer Science, page 364-373. Springer, (1997)Bit-Serial Digital Filter Implementation using a Custom C Compiler., and . APCCAS, page 534-537. IEEE, (2006)Graphics processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithm., , and . ISCAS (5), page 265-268. IEEE, (2004)The design of peak constrained least squares FIR filters with low complexity finite precision coefficients., and . ISCAS (2), page 605-608. IEEE, (2001)The Automatic Generation of Application Specific Processors., and . IWLS, page 161-165. (2002)Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations., and . EURASIP J. Adv. Signal Process., 2003 (6): 543-554 (2003)A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBitsTM., , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 222-231. Springer, (2002)Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms., and . VLSI, volume A-1 of IFIP Transactions, page 39-48. North-Holland, (1991)A C compiler for implementing FPGA based bit-serial DSP systems., and . FPT, page 305-308. IEEE, (2006)