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Eliminating Invalidation in Coherent-Cache Parallel Graph Reduction.

, and . PARLE, volume 817 of Lecture Notes in Computer Science, page 375-386. Springer, (1994)

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Modelling and Validation of Shared Memory Coherency Protocols., , and . Perform. Evaluation, 27/28 (4): 541-563 (1996)Eliminating Invalidation in Coherent-Cache Parallel Graph Reduction., and . PARLE, volume 817 of Lecture Notes in Computer Science, page 375-386. Springer, (1994)Efficient shared-memory support for parallel graph reduction., and . Future Gener. Comput. Syst., 12 (6): 481-503 (1997)The Parlay proxy manager - Architecture considerations., , and . Bell Labs Tech. J., 7 (3): 91-104 (2003)Cautions, Machine-Independent Performance Tuning for Shared-Memory Multiprocessors., , and . Euro-Par, Vol. I, volume 1123 of Lecture Notes in Computer Science, page 106-113. Springer, (1996)Performance Engineering with the UML Profile for Schedulability, Performance and Time: A Case Study., and . MASCOTS, page 67-75. IEEE Computer Society, (2004)Derivation and performance of a pipelined transaction processor., , and . SPDP, page 178-185. IEEE Computer Society, (1994)Service mediation standards., , , and . Bell Labs Tech. J., 7 (3): 77-90 (2003)Analysis of an Immune Algorithm for Protein Structure Prediction., , , and . Informatica (Slovenia), 32 (3): 245-251 (2008)Localtiy and False Sharing in Coherent-Cache Parallel Graph Reduction., and . PARLE, volume 694 of Lecture Notes in Computer Science, page 329-340. Springer, (1993)