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Disambiguation of "Yoshimura, Takeshi"

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EvFS: User-level, Event-Driven File System for Non-Volatile Memory.

, , and . HotStorage, USENIX Association, (2019)

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Tateo Yoshimura

Takeshi Morita

Tadasuke Yoshimura

Takeshi Morita

Takeshi Imamura

 

Other publications of authors with the same name

Genetic Algorithm based pipeline scheduling in high-level synthesis., and . ASICON, page 1-4. IEEE, (2013)Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis., , , and . ASICON, page 1-4. IEEE, (2015)Multiple-Reference Compression of RTP/UDP/IP Headers for Mobile Multimedia Communications., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (7): 1491-1500 (2002)Hierarchical-Analysis-Based Fast Chip-Scale Power Estimation Method for Large and Complex LSIs., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3458-3463 (2006)Power and resource aware scheduling with multiple voltages., , , , and . ASICON, page 1-4. IEEE, (2013)Floorplanning driven Network-on-Chip synthesis for 3-D SoCs., , , , and . ISCAS, page 1203-1206. IEEE, (2011)Mobility overlap-removal based leakage power aware scheduling in high-level synthesis., , , and . ISCAS, page 1745-1748. IEEE, (2013)Real-time video transport optimization using streaming agent over 3G wireless networks., , and . IEEE Trans. Multim., 7 (4): 777-785 (2005)A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition., , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2008)Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis., , and . ASP-DAC, page 237-242. IEEE, (2013)