( en | de | ru )

 

Disambiguation of "Glesner, Manfred"

Author of the publication

copydeleteadd this publication to your clipboard
Adaptable Image Processing System based on FPGA Modular Multi Kernel Instantiations.

, , , and . ReCoSoC, page 183-188. Univ. Montpellier II, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Manfred Glesner

Dieter Glesner

Sabine Glesner

Julia Glesner

Julia Glesner

 

Other publications of authors with the same name

A low power sinusoidal clock., and . ISCAS (4), page 108-111. IEEE, (2001)Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique., and . ISCAS, IEEE, (2006)Compact image compression using simplicial and ART neural systems with mixed signal implementations., , and . ISCAS (5), page 689-692. IEEE, (2003)Design of an efficient OFDM burst synchronization scheme., , and . ISCAS (3), page 449-452. IEEE, (2002)Field-programmable logic and application : reconfigurable computing is going mainstream : 12th international conference, FPL 2002, Montpellier, France, September 2-4, 2002 : proceedings, , , , and . Springer, (2002)Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans., , and . VLSI-SoC (Selected Papers), volume 200 of IFIP, page 149-164. Springer, (2003)A linearization technique for radio frequency CMOS Gilbert-type mixers., , , and . ICECS, page 1086-1089. IEEE, (2003)Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling., , , , and . ReCoSoC, page 7-14. Univ. Montpellier II, (2007)Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters., , , , and . VLSI-SoC, page 302-307. IEEE, (2006)Evaluation of state-of-the-art neural network customized hardware., and . Neurocomputing, 2 (5): 209-231 (1990)