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FPGA Implementations of Kernel Normalised Least Mean Squares Processors.

, , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 10 (4): 26:1-26:20 (2017)

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AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers., , , , , , and . CoRR, (2019)Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs., , , , and . FPT, page 1-9. IEEE, (2019)Compressing Low Precision Deep Neural Networks Using Sparsity-Induced Regularization in Ternary Networks., , , , and . ICONIP (2), volume 10635 of Lecture Notes in Computer Science, page 393-404. Springer, (2017)A Block Minifloat Representation for Training Deep Neural Networks., , , , and . ICLR, OpenReview.net, (2021)Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification., , , , , , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 16-28. Springer, (2018)Customizing Low-Precision Deep Neural Networks for FPGAs., , , , , and . FPL, page 97-100. IEEE Computer Society, (2018)AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (1): 115-128 (2020)SYQ: Learning Symmetric Quantization for Efficient Deep Neural Networks., , , and . CVPR, page 4300-4309. Computer Vision Foundation / IEEE Computer Society, (2018)Long Short-Term Memory for Radio Frequency Spectral Prediction and its Real-Time FPGA Implementation., , , , , , , and . MILCOM, page 1-9. IEEE, (2018)Super Efficient Neural Network for Compression Artifacts Reduction and Super Resolution., , , , and . WACV (Workshops), page 460-468. IEEE, (2024)