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CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples.

S. Voinigescu, S. Nicolson, M. Khanpour, K. Tang, K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, G. Eleftheriades, P. Schvan, and M. Yang. ISCAS, page 1971-1974. IEEE, (2007)

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Ilse Peters

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Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM Fiberoptics Applications.A. Zandieh, P. Schvan, and S. Voinigescu. IEEE J. Solid State Circuits, 54 (9): 2375-2387 (2019)Coherent Transceiver for High Speed Optical Communications: Opportunities and Challenges.S. Blais, Y. Greshishchev, P. Schvan, I. Betty, and D. McGhan. BCICTS, page 1-6. IEEE, (2019)A 24GS/s 6b ADC in 90nm CMOS.P. Schvan, J. Bach, C. Falt, P. Flemke, R. Gibbins, Y. Greshishchev, N. Ben-Hamida, D. Pollex, J. Sitch, S. Wang and 1 other author(s). ISSCC, page 544-545. IEEE, (2008)SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application.Y. Greshishchev, and P. Schvan. IEEE J. Solid State Circuits, 35 (9): 1353-1359 (2000)A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications.A. Zandieh, P. Schvan, and S. Voinigescu. BCICTS, page 52-55. IEEE, (2018)A 40 Gb/s transimpedance amplifier in 65 nm CMOS.S. Bashiri, C. Plett, J. Aguirre, and P. Schvan. ISCAS, page 757-760. IEEE, (2010)55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters.J. Hoffman, S. Shopov, P. Chevalier, A. Cathelin, P. Schvan, and S. Voinigescu. IEEE J. Solid State Circuits, 51 (9): 2040-2053 (2016)A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design.S. Voinigescu, M. Maliepaard, J. Showell, G. Babcock, D. Marchesan, M. Schroter, P. Schvan, and D. Harame. IEEE J. Solid State Circuits, 32 (9): 1430-1439 (1997)A 40GS/s 6b ADC in 65nm CMOS.Y. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida, D. Pollex, P. Schvan, and S. Wang. ISSCC, page 390-391. IEEE, (2010)A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory.Y. Greshishchev, D. Pollex, S. Wang, M. Besson, P. Flemeke, S. Szilagyi, J. Aguirre, C. Falt, N. Ben-Hamida, R. Gibbins and 1 other author(s). ISSCC, page 194-196. IEEE, (2011)

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Disambiguation of "Schvan, Peter"

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CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples.

Please choose a person to relate this publication to

Tanja Elisabeth Peters

Andre Peters

Jillian Petersen

Robert Martin Peterreins

Ilse Peters

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Schvan, Peter"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples.

Please choose a person to relate this publication to

Tanja Elisabeth Peters

Andre Peters

Jillian Petersen

Robert Martin Peterreins

Ilse Peters

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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Chicago
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CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples.