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Disambiguation of "Chatterjee, Sayan"

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Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme.

, , , , and . ISED, page 130-134. IEEE, (2012)

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Sayan Chakrabarty

Sayan Ghosh

Sayan Mitra

Gudrun Chatterjee

Amitava Chatterjee

 

Other publications of authors with the same name

Linear array pattern synthesis using restriction in search space for evolutionary algorithms: A comparative study., , , and . ReTIS, page 92-97. IEEE, (2015)An Online Pattern Based Activity Discovery: In Context of Geriatric Care., , , and . CISIM, volume 11703 of Lecture Notes in Computer Science, page 25-38. Springer, (2019)The Impact of AI Tool on Engineering at ANZ Bank An Emperical Study on GitHub Copilot within Coporate Environment., , , and . CoRR, (2024)Economy and Unemployment Due to COVID19: Secondary Research., , , , , and . IFIP TC12 ICIS, volume 623 of IFIP Advances in Information and Communication Technology, page 285-290. Springer International Publishing, (2020)Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme., , , , and . ISED, page 130-134. IEEE, (2012)A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications., , , , and . ISED, page 28-32. IEEE, (2012)Federated Learning for Intrusion Detection in IoT Security: A Hybrid Ensemble Approach., and . CoRR, (2021)Logic and Reduction Operation based Hardware Trojans in Digital Design., , and . ISOCC, page 342-343. IEEE, (2022)Design of High Gain Low-Noise Amplifier at X-Band Frequency., , and . ISDCS, page 1-3. IEEE, (2023)Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit., , , , and . CoRR, (2013)