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Estimating Error Rate in Defective Logic Using Signature Analysis.

, and . IEEE Trans. Computers, 56 (5): 650-661 (2007)

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Error Rate Estimation for Defective Circuits via Ones Counting., and . ACM Trans. Design Autom. Electr. Syst., 17 (1): 8:1-8:14 (2012)Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER)., and . VTS, page 59-66. IEEE Computer Society, (2008)Estimating Error Rate in Defective Logic Using Signature Analysis., and . IEEE Trans. Computers, 56 (5): 650-661 (2007)