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Rebalancing the core front-end through HPC code analysis.

, , , and . IISWC, page 128-137. IEEE Computer Society, (2016)

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High performance instruction fetch using software and hardware co-design.. Polytechnic University of Catalonia, Spain, (2002)Fetching instruction streams., , , and . MICRO, page 371-382. ACM/IEEE Computer Society, (2002)Task Superscalar: An Out-of-Order Task Pipeline., , , , , , , and . MICRO, page 89-100. IEEE Computer Society, (2010)Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors., , and . HiPEAC, volume 5952 of Lecture Notes in Computer Science, page 96-110. Springer, (2010)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications., , , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)Scalability Evaluation of a Polymorphic Register File: A CG Case Study., , , , and . ARCS, volume 6566 of Lecture Notes in Computer Science, page 13-25. Springer, (2011)Scaling HMMER Performance on Multicore Architectures., , , , and . CISIS, page 618-623. IEEE Computer Society, (2011)A Streaming Machine Description and Programming Model., , , , and . SAMOS, volume 4599 of Lecture Notes in Computer Science, page 107-116. Springer, (2007)Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors., , , , and . Euro-Par Workshops (2), volume 8806 of Lecture Notes in Computer Science, page 218-229. Springer, (2014)Parallelizing general histogram application for CUDA architectures., , , , and . ICSAMOS, page 11-18. IEEE, (2013)