Author of the publication

A case study of the task-based parallel wavefront pattern.

, , , , and . PARCO, volume 22 of Advances in Parallel Computing, page 65-72. IOS Press, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Parallel Pipeline on Heterogeneous Multi-processing Architectures., , , , , and . TrustCom/BigDataSE/ISPA (3), page 166-171. IEEE, (2015)978-1-4673-7952-6.An Advanced Compiler Framework for Non-Cache-Coherent Multiprocessors., , , , and . IEEE Trans. Parallel Distributed Syst., 13 (3): 241-259 (2002)Efficient heterogeneous matrix profile on a CPU + High Performance FPGA with integrated HBM., , , , , and . Future Gener. Comput. Syst., (2021)Lightweight asynchronous scheduling in heterogeneous reconfigurable systems., , , , , , and . J. Syst. Archit., (2022)Load sharing based on popularity in distributed video on demand systems., , , and . ICME (1), page 5-8. IEEE Computer Society, (2002)Towards a Software Transactional Memory for Heterogeneous CPU-GPU Processors., , , and . PARCO, volume 32 of Advances in Parallel Computing, page 708-717. IOS Press, (2017)Strategies for maximizing utilization on multi-CPU and multi-GPU heterogeneous architectures., , , and . J. Supercomput., 70 (2): 756-771 (2014)A New Strategy for Shape Analysis Based on Coexistent Link Sets., , , , and . PARCO, volume 33 of John von Neumann Institute for Computing Series, page 557-564. Central Institute for Applied Mathematics, Jülich, Germany, (2005)Lightweight Hardware Transactional Memory for GPU Scratchpad Memory., , , , and . IEEE Trans. Computers, 67 (6): 816-829 (2018)Simultaneous multiprocessing in a software-defined heterogeneous FPGA., , , , , , , and . J. Supercomput., 75 (8): 4078-4095 (2019)