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Disambiguation of "Jung, Seong-Ook"

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Noise-aware power optimization for on-chip interconnect.

, , , , and . ISLPED, page 108-113. ACM, (2000)

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Seong-Jung Kim

Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

 

Other publications of authors with the same name

An MTJ-based non-volatile flip-flop for high-performance SoC., , , , , and . I. J. Circuit Theory and Applications, 42 (4): 394-406 (2014)Transistor sizing for reliable domino logic design in dual threshold voltage technologies., , and . ACM Great Lakes Symposium on VLSI, page 133-138. ACM, (2001)Low-swing clock domino logic incorporating dual supply and dual threshold voltages., , and . DAC, page 467-472. ACM, (2002)Noise-aware power optimization for on-chip interconnect., , , , and . ISLPED, page 108-113. ACM, (2000)A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface., , and . IEEE Trans. Consumer Electronics, 56 (4): 2400-2405 (2010)MTJ based non-volatile flip-flop in deep submicron technology., , , , , and . ISOCC, page 424-427. IEEE, (2011)SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (8): 2063-2072 (2017)Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (8): 2963-2972 (2019)Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2737-2747 (2017)SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (6): 1538-1545 (2015)