( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters.

, , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (9): 2552-2560 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Dustin Stansbury

Ian Dunwell

Dustin Lange

Dustin Flock

Dustin McIntire

 

Другие публикации лиц с тем же именем

A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on., , , , , и . CICC, стр. 1-4. IEEE, (2012)All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (9): 2552-2560 (2017)A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS., и . ISCAS, стр. 205-208. IEEE, (2010)A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC., , , и . ISCAS, стр. 1320-1323. IEEE, (2014)Modeling Oscillator Injection Locking Using the Phase Domain Response., и . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (11): 2823-2833 (2013)Channel characterization using jitter measurements., , и . ISCAS, стр. 2666-2669. IEEE, (2013)24 GHz Low-Noise Amplifiers using High Q Series-Stub Transmission Lines in 0.18µm CMOS., и . CCECE, стр. 1918-1921. IEEE, (2006)Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver., и . CICC, стр. 1-4. IEEE, (2010)A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS., , , , , , , , , и 3 other автор(ы). ISSCC, стр. 482-484. IEEE, (2019)