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Disambiguation of "Jaleel, Aamer"

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Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies.

, , , , and . MICRO, page 151-162. IEEE Computer Society, (2010)

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Jaleel Akhtar

Hassan Jaleel

 

Other publications of authors with the same name

Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores., , , and . IEEE Comput. Archit. Lett., 16 (1): 56-59 (2017)DUCATI: High-performance Address Translation by Extending TLB Reach of GPU-accelerated Systems., , and . ACM Trans. Archit. Code Optim., 16 (1): 6:1-6:24 (2019)P-OPT: Practical Optimal Cache Replacement for Graph Analytics., , , and . HPCA, page 668-681. IEEE, (2021)BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches., , and . ISCA, page 198-210. ACM, (2015)RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks., , , , , , and . DAC, page 7:1-7:6. ACM, (2017)In-Line Interrupt Handling for Software-Managed TLBs., and . ICCD, page 62-67. IEEE Computer Society, (2001)Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions., and . HPCA, page 191-200. IEEE Computer Society, (2005)IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations., , , , , and . MICRO, page 1163-1177. ACM, (2023)ExTensor: An Accelerator for Sparse Tensor Algebra., , , , , , , and . MICRO, page 319-333. ACM, (2019)In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs)., and . IEEE Trans. Computers, 55 (5): 559-574 (2006)