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16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC.

B. Vaz, A. Lynam, B. Verbruggen, A. Laraba, C. Mesadri, A. Boumaalif, J. McGrath, U. Kamath, R. Torre, A. Manlapat, D. Breathnach, C. Erdmann, and B. Farley. ISSCC, page 276-277. IEEE, (2017)

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Fathollah Asmar

Muhammad Tauseef Asmat

Asma Ounnas

Asma Mehiaoui

Asma Maalej

Other publications of authors with the same name

A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET.J. Hudner, D. Carey, R. Casey, K. Hearne, P. de Abreu Farias Neto, I. Chlis, M. Erett, C. Poon, A. Laraba, H. Zhang and 5 other author(s). VLSI Circuits, page 47-48. IEEE, (2018)Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs.A. Laraba, H. Stratigopoulos, S. Mir, H. Naudet, and C. Forel. European Test Symposium, page 1-6. IEEE Computer Society, (2012)Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique.A. Laraba, H. Stratigopoulos, S. Mir, and H. Naudet. IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (10): 2391-2400 (2015)16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC.B. Vaz, A. Lynam, B. Verbruggen, A. Laraba, C. Mesadri, A. Boumaalif, J. McGrath, U. Kamath, R. Torre, A. Manlapat and 3 other author(s). ISSCC, page 276-277. IEEE, (2017)Reduced code linearity testing of pipeline adcs in the presence of noise.A. Laraba, H. Stratigopoulos, S. Mir, H. Naudet, and G. Bret. VTS, page 1-6. IEEE Computer Society, (2013)A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs.G. Renaud, M. Barragán, A. Laraba, H. Stratigopoulos, S. Mir, H. Gall, and H. Naudet. J. Electron. Test., 32 (4): 407-421 (2016)A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET.C. Poon, W. Zhang, J. Cho, S. Ma, Y. Wang, Y. Cao, A. Laraba, E. Ho, W. Lin, Z. Wu and 3 other author(s). IEEE J. Solid State Circuits, 57 (4): 1199-1210 (2022)A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET.C. Poon, W. Zhang, J. Cho, S. Ma, Y. Wang, Y. Cao, A. Laraba, E. Ho, W. Lin, Z. Wu and 3 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)Reduced-Code Linearity Testing of Pipeline ADCs.A. Laraba, H. Stratigopoulos, S. Mir, H. Naudet, and G. Bret. IEEE Des. Test, 30 (6): 80-88 (2013)

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Disambiguation of "Laraba, Asma"

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16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC.

Please choose a person to relate this publication to

Fathollah Asmar

Muhammad Tauseef Asmat

Asma Ounnas

Asma Mehiaoui

Asma Maalej

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Laraba, Asma"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC.

Please choose a person to relate this publication to

Fathollah Asmar

Muhammad Tauseef Asmat

Asma Ounnas

Asma Mehiaoui

Asma Maalej

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC.