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A 12.5Gb/s active-inductor based transmitter for I/O applications., , , , and . ECCTD, page 186-189. IEEE, (2011)Multi-step counting ADC., , and . MWSCAS, page 17-20. IEEE, (2014)A noise-coupled time-interleaved delta-sigma modulator with shifted loop delays., , , , and . ISCAS, page 2045-2048. IEEE, (2015)0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique., , , , , , , and . CICC, page 1-4. IEEE, (2019)An Amplifier-Free 0-2 SAR-VCO MASH ΔΣ ADC., , , , and . ISCAS, page 1-5. IEEE, (2019)A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer., , , , , and . MWSCAS, page 145-148. IEEE, (2018)A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (7): 2440-2453 (2019)Digital Correction of DAC Nonlinearity in Multi-Bit Feedback A/D Converters: Invited tutorial., , , and . CICC, page 1-8. IEEE, (2020)Sequential interstage correlated double sampling: A switched-capacitor technique for high accuracy systems., , , , and . MWSCAS, page 262-265. IEEE, (2014)A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 347-351 (2019)