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An Efficient Parallelized L7-Filter Design for Multicore Servers.

, , and . IEEE/ACM Trans. Netw., 20 (5): 1426-1439 (2012)

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VLSI Performance of Multistage Interconnection Network Using 4*4 Switches., and . ICDCS, page 606-613. IEEE Computer Society, (1982)Finite Buffer Analysis of Multistage Interconnection Networks., and . IEEE Trans. Computers, 43 (2): 243-247 (1994)Reliability Simulation of Multiprocessor Systems., and . ICPP, page 591-598. IEEE Computer Society Press, (1985)Extending Multistage Interconnection Networks for Multitasking., and . ICPP (1), page 151-158. CRC Press, (1992)Bandwidth Availability of Multiple-Bus Multiprocessors., and . IEEE Trans. Computers, 34 (10): 918-926 (1985)Fair Scheduling in Internet Routers., and . IEEE Trans. Computers, 51 (6): 686-701 (2002)Performance Evaluation of a Dataflow Architecture., and . IEEE Trans. Computers, 39 (5): 615-627 (1990)Design and Performance of Generalized Interconnection Networks., and . IEEE Trans. Computers, 32 (12): 1081-1090 (1983)Enhancing Network Processor Simulation Speed with Statistical Input Sampling., , , , and . HiPEAC, volume 3793 of Lecture Notes in Computer Science, page 68-83. Springer, (2005)A Network Processor-Based, Content-Aware Switch., , , and . IEEE Micro, 26 (3): 72-84 (2006)