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Functional Text Pattern Generation for Asynchronous Circuits.

, , and . ISCAS, page 1519-1522. IEEE, (1993)

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Histogram Based Testing Strategy for ADC., , and . ATS, page 51-54. IEEE, (2006)A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter., , , and . APCCAS, page 1260-1263. IEEE, (2006)A scalable sorting architecture based on maskable WTA/MAX circuit., , and . ISCAS (4), page 209-212. IEEE, (2002)System level design of a spatio-temporal video resampling architecture., , , and . ISCAS, page 2797-2800. IEEE, (2008)A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques., and . ISCAS (3), page 1972-1975. IEEE, (2005)A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach., , , and . ISLPED, page 252-256. ACM, (2004)A new level converter for low-power applications., , and . ISCAS (1), page 113-116. IEEE, (2001)A microfluidic and potentiostatic sensor integrated with neopterin-imprinted poly(ethylene-c0-vinyl alcohol) based electrode., , , , , , , and . NEMS, page 575-578. IEEE, (2011)Performance-directed compaction for VLSI symbolic layouts., , , and . Comput. Aided Des., 27 (1): 65-74 (1995)An iterative enhanced super-resolution system with edge-dominated interpolation and adaptive enhancements., , , and . EURASIP J. Adv. Signal Process., (2015)