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11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip., , , , , , , , , and 22 other author(s). ISSCC, page 214-215. IEEE, (2024)A Digital Neurosynaptic Core Using Event-Driven QDI Circuits., , , , , and . ASYNC, page 25-32. IEEE Computer Society, (2012)Variability in 3-D integrated circuits., , , , and . CICC, page 659-662. IEEE, (2008)Design and Tool Flow of IBM's TrueNorth: an Ultra-Low Power Programmable Neurosynaptic Chip with 1 Million Neurons.. ISPD, page 59-60. ACM, (2016)A Level-Crossing Flash Asynchronous Analog-to-Digital Converter., , and . ASYNC, page 12-22. IEEE Computer Society, (2006)Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores., , , , , , , , , and 6 other author(s). IJCNN, page 1-10. IEEE, (2013)TrueNorth: Accelerating From Zero to 64 Million Neurons in 10 Years., , , , , , , , , and 18 other author(s). Computer, 52 (5): 20-29 (2019)Building block of a programmable neuromorphic substrate: A digital neurosynaptic core., , , , , , , , , and 2 other author(s). IJCNN, page 1-8. IEEE, (2012)A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm., , , , , and . CICC, page 1-4. IEEE, (2011)TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip., , , , , , , , , and 8 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (10): 1537-1557 (2015)