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Disambiguation of "Strollo, Antonio G. M."

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A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS.

, , , , , and . IEEE J. Solid State Circuits, 43 (6): 1403-1413 (2008)

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M G Weller

G M Klump

Angelo Strollo

Angelo Strollo

Angelo Strollo

 

Other publications of authors with the same name

Constrained piecewise polinomial approximation for hardware implementation of elementary functions., , , , and . ICECS, page 698-701. IEEE, (2008)Low error truncated multipliers for DSP applications., , , , and . ICECS, page 29-32. IEEE, (2008)Low-Power Hardware Implementation of Least-Mean-Square Adaptive Filters Using Approximate Arithmetic., , , , and . CSSP, 38 (12): 5606-5622 (2019)Dual-Tree Error Compensation for High Performance Fixed-Width Multipliers., , and . IEEE Trans. Circuits Syst. II Express Briefs, 52-II (8): 501-507 (2005)A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (7): 1921-1928 (2008)New clock-gating techniques for low-power flip-flops., , and . ISLPED, page 114-119. ACM, (2000)Approximate adder with output correction for error tolerant applications and Gaussian distributed inputs., , , , , and . ISCAS, page 1970-1973. IEEE, (2016)Low-power Implementation of LMS Adaptive Filters Using Scalable Rounding., , , , and . ICECS, page 1-4. IEEE, (2020)New design of squarer circuits using Booth encoding and folding techniques., , and . ICECS, page 193-196. IEEE, (2001)Approximate computing in the nanoscale era., and . ICICDT, page 21-24. IEEE, (2018)