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INFORMER: An integrated framework for early-stage memory robustness analysis.

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An Approach to the Development of a IDDQ Testable Cell Library., , , , and . DFT, page 46-54. IEEE Computer Society, (1994)An investigation on the relation between digital circuitry characteristics and power supply noise spectrum in mixed-signal CMOS integrated circuits., , , and . Microelectron. J., 36 (1): 77-84 (2005)New redundant logic design concept for high noise and low voltage scenarios., , , , , and . Microelectron. J., 42 (12): 1359-1369 (2011)Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22 nm., , , , and . Microelectron. J., 45 (10): 1342-1347 (2014)Experimental Study of Artificial Neural Networks Using a Digital Memristor Simulator., , , , and . IEEE Trans. Neural Networks Learn. Syst., 29 (10): 5098-5110 (2018)Data Dependence of Delay Distribution for a Planar Bus., , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 409-418. Springer, (2008)Design and implementation of a 5×5 trits multiplier in a quasi-adiabatic ternary CMOS logic., and . IEEE J. Solid State Circuits, 33 (7): 1111-1116 (1998)Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells., , , , and . Integr., 45 (3): 246-252 (2012)Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions Impact., , , and . IEEE Access, (2022)Parkinson's Treatment Emulation Using Asynchronous Cellular Neural Networks., , , and . LASCAS, page 1-4. IEEE, (2023)