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Disambiguation of "Sakare, Mahendra"

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Design of a PRBS generator and a serializer using active inductor employed CML latch.

, , , and . MWSCAS, page 802-805. IEEE, (2021)

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Mahendra Nath

Mahendra Samarawickrama

Mahendra Prasad

Mahendra Doshi

Mahendra Kothari

 

Other publications of authors with the same name

A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks., , , , , and . Circuits Syst. Signal Process., 42 (11): 6813-6828 (November 2023)A low power 8 × 27-1 PRBS generator using Exclusive-OR gate merged D flip-flops., , , and . MWSCAS, page 779-782. IEEE, (2021)Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits., , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (8): 768-772 (2016)A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOs., , , , , and . APCCAS, page 1-5. IEEE, (2023)Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (7): 993-1003 (2023)Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons., , , and . Integr., (March 2024)Design of a PRBS generator and a serializer using active inductor employed CML latch., , , and . MWSCAS, page 802-805. IEEE, (2021)Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism., , , and . NorCAS, page 1-7. IEEE, (2023)A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs.. IEEE Trans. Circuits Syst. II Express Briefs, 64-II (8): 927-931 (2017)Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse., , , and . MWSCAS, page 445-448. IEEE, (2021)