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A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder., , , , and . ASICON, page 1-4. IEEE, (2013)A 2D mesh NoC with self-configurable and shared-FIFOs routers., , , , and . ASICON, page 1-4. IEEE, (2013)A fast multi-core virtual platform and its application on software development., , , , and . ASICON, page 1-4. IEEE, (2013)Low-complexity two-stage timing acquisition scheme for UWB communications., , and . WTS, page 53-56. IEEE, (2008)An improved coarse synchronization scheme in 3GPP LTE downlink OFDM systems., , , , and . ISCAS, page 1516-1519. IEEE, (2012)A common flexible architecture for Turbo/LDPC codes., , , , and . ISOCC, page 54-57. IEEE, (2011)A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array., , , , , , , , , and 4 other author(s). ISSCC, page 56-57. IEEE, (2013)A low power register file with asynchronously controlled read-isolation and software-directed write-discarding., , , , and . ISCAS, page 349-352. IEEE, (2013)Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications., , , , and . ASICON, page 465-468. IEEE, (2011)Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (4): 1089-1093 (2020)