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A parallel LSI architecture for LDPC decoder improving message-passing schedule.

K. Shimizu, T. Ishikawa, N. Togawa, T. Ikenaga, and S. Goto. ISCAS, IEEE, (2006)

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Juhei Goto

Satoshi Ejima

Toshifumi Goto

Hiroshi Goto

Satoshi Okawa

Other publications of authors with the same name

High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications.G. He, D. Zhou, W. Fei, Z. Chen, J. Zhou, and S. Goto. IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 76-89 (2014)A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application.Z. Chen, X. Zhao, X. Peng, D. Zhou, and S. Goto. IPSJ Trans. Syst. LSI Des. Methodol., (2010)An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard.Y. Fan, J. Wang, T. Ikenaga, Y. Tsunoo, and S. Goto. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (1): 12-21 (2008)Dynamic Check Message Majority-Logic Decoding Algorithm for Non-binary LDPC Codes.Y. Lu, X. Peng, G. Tian, and S. Goto. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (6): 1356-1364 (2014)Human Detection Method Based on Non-Redundant Gradient Semantic Local Binary Patterns.J. Xu, N. Jiang, W. Yu, H. Sun, and S. Goto. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (8): 1735-1742 (2015)An Integrated Hole-Filling Algorithm for View Synthesis.W. Yu, W. Wang, M. Wang, and S. Goto. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (6): 1306-1314 (2013)HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis.Z. Liu, Y. Song, M. Shao, S. Li, L. Li, S. Ishiwata, M. Nakagawa, S. Goto, and T. Ikenaga. IEEE J. Solid State Circuits, 44 (2): 594-608 (2009)A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder.X. Chen, P. Liu, D. Zhou, J. Zhu, X. Pan, and S. Goto. IEICE Trans. Electron., 93-C (3): 253-260 (2010)A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder.J. Zhu, D. Zhou, and S. Goto. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2612-2622 (2013)Low-Power Motion Estimation Processor with 3D Stacked Memory.S. Zhang, J. Zhou, D. Zhou, S. Kimura, and S. Goto. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (7): 1431-1441 (2015)

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Disambiguation of "Goto, Satoshi"

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A parallel LSI architecture for LDPC decoder improving message-passing schedule.

Please choose a person to relate this publication to

Juhei Goto

Satoshi Ejima

Toshifumi Goto

Hiroshi Goto

Satoshi Okawa

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Goto, Satoshi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A parallel LSI architecture for LDPC decoder improving message-passing schedule.

Please choose a person to relate this publication to

Juhei Goto

Satoshi Ejima

Toshifumi Goto

Hiroshi Goto

Satoshi Okawa

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A parallel LSI architecture for LDPC decoder improving message-passing schedule.