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Registers Size Influence on Vector Architectures., , and . VECPAR, volume 1573 of Lecture Notes in Computer Science, page 439-451. Springer, (1998)DVINO: A RISC-V Vector Processor Implemented in 65nm Technology., , , , , , , , , and 33 other author(s). DCIS, page 1-6. IEEE, (2022)Large Free Software Projects and Bugzilla. Proceedings of the Linux Symposium, page 471-480. Ottawa, Canada, (2003)Dynamic zero compression for cache energy reduction., , and . MICRO, page 214-220. ACM/IEEE Computer Society, (2000)A partitioned instruction queue to reduce instruction wakeup energy., , , , and . Int. J. High Perform. Comput. Netw., 1 (4): 153-161 (2004)Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology., , , , , , , , , and 38 other author(s). DCIS, page 1-6. IEEE, (2023)A Performance Study of Out-of-order Vector Architectures and Short Registers., , and . International Conference on Supercomputing, page 37-44. ACM, (1998)Report of the 1st Workshop on Generative AI and Law., , , , , , , , , and 25 other author(s). CoRR, (2023)A Simple Low-Energy Instruction Wakeup Mechanism., , , , and . ISHPC, volume 2858 of Lecture Notes in Computer Science, page 99-112. Springer, (2003)A literature review for large-scale health information system project planning, implementation and evaluation., , , and . Int. J. Medical Informatics, (2017)