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An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM., , , , , , , , , and 7 other author(s). A-SSCC, page 139-142. IEEE, (2018)A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller., , , , , , , , , and 19 other author(s). ISSCC, page 384-386. IEEE, (2019)Design of Processing-"Inside"-Memory Optimized for DRAM Behaviors., , , , , and . IEEE Access, (2019)A Reproducing Kernel Hilbert Space Framework for ITL., , , and . Information Theoretic Learning, Springer, (2010)Estimation of symmetric chi-square divergence for point processes., , , and . ICASSP, page 2016-2019. IEEE, (2011)Quantification of inter-trial non-stationarity in spike trains from periodically stimulated neural cultures., and . ICASSP, page 5442-5445. IEEE, (2010)System Architecture and Software Stack for GDDR6-AiM., , , , , , , , , and 31 other author(s). HCS, page 1-25. IEEE, (2022)A Closed Form Solution for Multiple-Input Spike Based Adaptive Filters., , , and . IJCNN, page 2064-2068. IEEE, (2007)Quantification of inter-trial non-stationarity in spike trains from periodically stimulated neural cultures., and . ICASSP, page 5442-5445. IEEE, (2010)Do Trace Cache, Value Prediction and Prefetching Improve SMT Throughput?., , and . ARCS, volume 3894 of Lecture Notes in Computer Science, page 232-251. Springer, (2006)