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On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms., и . VLSI-SoC (Selected Papers), том 464 из IFIP Advances in Information and Communication Technology, стр. 110-128. Springer, (2014)Correct-by-construction generation of device drivers based on RTL testbenches., , , и . DATE, стр. 1500-1505. IEEE, (2009)Logic-level analysis of high-level faults., и . ACM Great Lakes Symposium on VLSI, стр. 100-103. ACM, (2004)A testbench specification language for SystemC verification., и . CODES+ISSS, стр. 333-342. ACM, (2012)A cosimulation methodology for HW/SW validation and performance estimation., , , и . ACM Trans. Design Autom. Electr. Syst., 14 (2): 23:1-23:32 (2009)Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level., , и . VLSI-SoC (Selected Papers), том 661 из IFIP Advances in Information and Communication Technology, стр. 71-92. Springer, (2021)Exploiting assertions mining and fault analysis to guide RTL-level approximation., , , и . DATE, стр. 1-2. IEEE, (2023)UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration., , , , и . IEEE Trans. Computers, 62 (2): 225-241 (2013)A time-window based approach for dynamic assertions mining on control signals., , и . VLSI-SoC, стр. 246-251. IEEE, (2015)At-Speed Functional Verification of Programmable Devices., , и . DFT, стр. 386-394. IEEE Computer Society, (2004)