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Disambiguation of "Lewis, David M."

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3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration.

, , , , , , , , , , , , , , , , , and . ISSCC, page 54-55. IEEE, (2017)

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J. D. Lewis-Williams

David M Eche

David M Eche

David M Stec

David M Allen

 

Other publications of authors with the same name

A compiled-code hardware accelerator for circuit simulation.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (5): 555-565 (1992)Circuit design of routing switches., and . FPGA, page 19-28. ACM, (2002)Highly Selective Änalog" Filters Using Delta Sigma Based IIR Filtering., , and . ISCAS, page 1302-1305. IEEE, (1993)Automated field-programmable compute accelerator design using partial evaluation., and . FCCM, page 145-154. IEEE Computer Society, (1997)A hierarchical compiled code event-driven logic simulator.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (6): 726-737 (1991)A multiple-strength multiple-delay compiled-code logic simulator., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (12): 1937-1946 (1993)Spatial Timing Analysis With Exact Propagation of Delay and Application to FPGA Performance., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (11): 2153-2166 (2019)Procedural Texture Mapping on FPGAs., and . FPGA, page 112-120. ACM, (1999)The StratixTM routing and logic architecture., , , , , , , , , and 4 other author(s). FPGA, page 12-20. ACM, (2003)Using sparse crossbars within LUT., and . FPGA, page 59-68. ACM, (2001)