Author of the publication

A single chip VLSI architecture for a real time stereo vision processor.

, , , and . ICASSP, page 1965-1968. IEEE, (1988)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

VLSI architectures for dynamic time warping using systolic arrays., , , and . ICASSP, page 778-781. IEEE, (1984)VLSI Architecture for a one chip video median filter., , , and . ICASSP, page 1001-1004. IEEE, (1985)A single chip VLSI architecture for a real time stereo vision processor., , , and . ICASSP, page 1965-1968. IEEE, (1988)Real-time VLSI architecture for geometric image transformations., , , and . VCIP, volume 1360 of SPIE Proceedings, SPIE, (1990)Memory-I/O tradeoff and VLSI implementation of lapped transforms for image processing., and . ICASSP (1), page 393-396. IEEE Computer Society, (1993)From image coding to multimedia: Algorithms and architectures for a revolution.. Microprocess. Microprogramming, 35 (1-5): 3 (1992)A Generalized Precompiling scheme for Surviving Path Memory Management in Viterbi decoders., and . ISCAS, page 1579-1582. IEEE, (1993)A single chip video rate 16×16 discrete cosine transform., , , , and . ICASSP, page 805-808. IEEE, (1986)VLSI architectures for video compression-a survey., , and . Proc. IEEE, 83 (2): 220-246 (1995)Optimization of Real-Time VLSI Architectures for Distributed Arithmetic-Based Algorithms: Application to HDTV Filters., and . ISCAS, page 223-226. IEEE, (1994)