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Post-Layout Simulation Driven Analog Circuit Sizing.

X. Gao, H. Zhang, S. Ye, M. Liu, D. Pan, L. Shen, R. Wang, Y. Lin, and R. Huang. CoRR, (2023)

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Lin Lin

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Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net-Order Exploration in Detailed Routing.Y. Lin, T. Qu, Z. Lu, Y. Su, and Y. Wei. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (9): 3132-3142 (2022)Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures.Y. Lin, B. Yu, M. Li, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (8): 1574-1587 (2018)A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion.M. Li, B. Yu, Y. Lin, X. Xu, W. Li, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (9): 1585-1598 (2019)Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection.Y. Lin, M. Li, Y. Watanabe, T. Kimura, T. Matsunawa, S. Nojima, and D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1900-1913 (2019)Introduction to the Special Issue on Machine Learning for CAD/EDA.Y. Lin, A. Ziv, and H. Ren. ACM Trans. Design Autom. Electr. Syst., 28 (2): 14:1-14:2 (March 2023)Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview.J. Yan, X. Liu, R. Cheng, and Y. Lin. CoRR, (2022)Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing.T. Qu, Y. Lin, Z. Lu, Y. Su, and Y. Wei. DATE, page 1815-1820. IEEE, (2021)DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting.P. Liao, S. Liu, Z. Chen, W. Lv, Y. Lin, and B. Yu. DATE, page 939-944. IEEE, (2022)FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler.S. Liu, P. Liao, R. Zhang, Z. Chen, W. Lv, Y. Lin, and B. Yu. DATE, page 760-765. IEEE, (2022)An Efficient Task-Parallel Pipeline Programming Framework.C. Chiu, Z. Xiong, Z. Guo, T. Huang, and Y. Lin. HPC Asia, page 95-106. ACM, (2024)

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Disambiguation of "Lin, Yibo"

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Post-Layout Simulation Driven Analog Circuit Sizing.

Please choose a person to relate this publication to

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

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BibSonomy

Disambiguation of "Lin, Yibo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Post-Layout Simulation Driven Analog Circuit Sizing.

Please choose a person to relate this publication to

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

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Post-Layout Simulation Driven Analog Circuit Sizing.