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Disambiguation of "Paredes, José"

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Leveraging Probabilistic Existential Rules for Adversarial Deduplication.

, , , and . PRUV@IJCAR, volume 2157 of CEUR Workshop Proceedings, CEUR-WS.org, (2018)

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Humberto Jorge José

Emiliane Paredes

Liliana Paredes

Nadine José Gonzalez

José Navarrete

 

Other publications of authors with the same name

Leveraging Probabilistic Existential Rules for Adversarial Deduplication., , , and . PRUV@IJCAR, volume 2157 of CEUR Workshop Proceedings, CEUR-WS.org, (2018)NetDER: An Architecture for Reasoning About Malicious Behavior., , , and . Inf. Syst. Frontiers, 23 (1): 185-201 (2021)First Steps towards Data-Driven Adversarial Deduplication., , , and . Inf., 9 (8): 189 (2018)The HEIC application framework for implementing XAI-based socio-technical systems., , , and . Online Soc. Networks Media, (2022)Detecting malicious behavior in social platforms via hybrid knowledge- and data-driven systems., , , and . Future Gener. Comput. Syst., (2021)On the Importance of Domain-specific Explanations in AI-based Cybersecurity Systems (Technical Report)., , , and . CoRR, (2021)Improvements to the Robust Transform Based on the Weighted Median Operator Algorithm., , and . CLEI Selected Papers, volume 349 of Electronic Notes in Theoretical Computer Science, page 81-102. Elsevier, (2020)5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth., , , , , , , , , and 10 other author(s). ISSCC, page 96-97. IEEE, (2014)3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4., , , , , , , , , and 4 other author(s). ISSCC, page 50-51. IEEE, (2017)The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (1): 91-101 (2018)