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Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design.

, , and . FCCM, page 218-226. IEEE, (2019)

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P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs., , and . CoRR, (2017)P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs., , and . FPGA, page 147-152. ACM, (2018)Extern Objects in P4: an ROHC Header Compression Scheme Case Study., , , and . NetSoft, page 517-522. IEEE, (2018)Design Principles for Packet Deparsers on FPGAs., , , and . FPGA, page 280-286. ACM, (2021)Extern Objects in P4: an ROHC Compression Case Study., , , and . CoRR, (2016)Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design., , and . FCCM, page 218-226. IEEE, (2019)Unleashing the Power of FPGAs as Programmable Switches., , , , and . FPGA, page 311. ACM, (2020)One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing., , , , and . ICNP, page 440-441. IEEE Computer Society, (2018)Bridging the Gap: FPGAs as Programmable Switches., , , , and . HPSR, page 1-7. IEEE, (2020)Area-oriented iterative method for Design Space Exploration with High-Level Synthesis., and . LASCAS, page 1-4. IEEE, (2015)