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Disambiguation of "Takemura, Riichiro"

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A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.

, , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 36 (11): 1721-1727 (2001)

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Other publications of authors with the same name

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router., , , , and . IEEE J. Solid State Circuits, 40 (4): 853-861 (2005)A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 45 (4): 869-879 (2010)A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing., , , , and . IEICE Trans. Electron., 95-C (4): 600-608 (2012)Low-Voltage Limitations and Challenges of Memory-Rich Nano-Scale CMOS LSIs., and . ICECS, page 739-742. IEEE, (2007)SPRAM (SPin-transfer torque RAM) design and its impact on digital systems., , , and . ICECS, page 1011-1014. IEEE, (2007)2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read., , , , , , , , , and 4 other author(s). ISSCC, page 480-617. IEEE, (2007)Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays., , , , and . ISSCC, page 142-143. IEEE, (2009)Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM., , , , , and . IEEE J. Solid State Circuits, 41 (1): 107-112 (2006)Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays., , , , and . IEICE Trans. Electron., 95-C (4): 594-599 (2012)Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device., , , , , , and . ISCAS, page 2299-2302. IEEE, (2012)